The FlashArray//XR2 and //XR3 architectures utilize dedicated NVRAM modules to provide the non-volatile write cache necessary for acknowledging writes safely before they are destaged to flash. These chassis are equipped with multiple NVRAM bays (labeled NVB0 through NVB3).

For standard configurations, specifically the //X10, //X20, and //X50 models, the system requires a redundant pair of NVRAM modules to function. These are always installed in NVRAM bays 0 and 1.

Bays 0 and 1 form the primary high-availability pair. If one fails, the other retains the data, and the system can continue to operate (though often in write-through mode or with alerts).

Higher-end models like the //X70 and //X90 populate all four bays (0-3) to provide the larger write buffer required for their higher throughput capabilities.

However, since the question asks which bays are always populated (i.e., the minimum requirement for the platform to function across the board), the answer is the foundational pair in slots 0 and 1. An Implementation Engineer must ensure these specific slots are populated first during any chassis maintenance or upgrade.

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